Flash and other types of nonvolatile electronic memory devices are constructed of memory cells that are individually operative to individually store and provide access to binary information or data. In typical nonvolatile electronic memory architectures, each memory cell has a MOS transistor structure including a source, a drain, and a channel formed in a substrate, with a stacked gate structure overlying the channel. The individual memory cells are organized into individually addressable units or groups such as bytes, which comprise eight cells, or words, which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state. The bytes or words of memory cells are accessed for read, program, or erase operations through address decoding circuitry using conductive interconnects typically referred to as wordlines and bitlines.
FIG. 1 is a cross-sectional view of just one of many conventional memory cells. The cell 10 is formed on a substrate 12, having a heavily doped drain region 14 and source region 16 embedded therein. The drain and source regions 14 and 16 typically contain deep diffused regions 18 and 20 that are lightly doped, and shallow diffused regions 22 and 24 that are more highly doped. A channel region 26 separates the drain region 14 from the source region 16. The cell 10 typically is characterized by a vertical gate stack, and the conventional gate stack configuration depicted in FIG. 1 includes a tunnel oxide layer 28, a floating gate 30 over the tunnel oxide layer, an interlevel dielectric layer 32, and a control gate 34 over the interlevel dielectric layer. Numerous other gate stack configurations for flash memory devices are also known in the art.
During IC fabrication, a conductive contact such as a metal silicide is deposited or otherwise formed on the control gate 34, source region 16, and/or the drain region 14 to access the memory device and allow interconnections between the memory device and other IC devices. At times there may be some exposed IC elements that should not be covered with a metal silicide or other contact material. For example, FIG. 2 is a top schematic view of an IC device having doped junctions 40 that are formed in a vertical direction (as illustrated), with horizontal word line control gates 42 formed over the junctions 40. Areas between the doped junctions 40 may include exposed silicon 44. Depositing metal silicide or other contact material onto the exposed silicon 44 could be detrimental to the device performance. FIG. 3 is a cross-sectional view along line 3-3 in FIG. 2, and depicts contact material 46 deposited onto the doped junctions 40 and also onto the adjacent exposed silicon 44. In this case, indiscriminately forming metal silicide or other contact material 46 may create an electrical short between the junctions 40 or produce other undesirable effects.
Accordingly, it is desirable to provide a method that enables selective formation of metal silicide or other contact material to avoid metal deposition in undesirable memory device regions. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.